167 lines
5.6 KiB
Go
167 lines
5.6 KiB
Go
// Copyright 2022 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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// This file contains pin mapping information that is specific to the Allwinner
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// H2+ and H3 model.
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package allwinner
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import (
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"strconv"
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"strings"
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"periph.io/x/conn/v3/pin"
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"periph.io/x/host/v3/sysfs"
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)
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// mappingH3 describes the mapping of the H3 processor GPIO pins to their
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// functions. The mappings source is the official H3 Datasheet, version 1.0,
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// page 74 (chapter 3.2 GPIO Multiplexing Functions).
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// http://dl.linux-sunxi.org/H3/Allwinner_H3_Datasheet_V1.0.pdf
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var mappingH3 = map[string][5]pin.Func{
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"PA0": {"UART2_TX", "JTAG_MS", "", "", "PA_EINT0"},
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"PA1": {"UART2_RX", "JTAG_CK", "", "", "PA_EINT1"},
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"PA2": {"UART2_RTS", "JTAG_DO", "", "", "PA_EINT2"},
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"PA3": {"UART2_CTS", "JTAG_DI", "", "", "PA_EINT3"},
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"PA4": {"UART0_TX", "", "", "", "PA_EINT4"},
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"PA5": {"UART0_RX", "PWM0", "", "", "PA_EINT5"},
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"PA6": {"SIM_PWREN", "PWM1", "", "", "PA_EINT6"},
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"PA7": {"SIM_CK", "", "", "", "PA_EINT7"},
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"PA8": {"SIM_DATA", "", "", "", "PA_EINT8"},
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"PA9": {"SIM_RST", "", "", "", "PA_EINT9"},
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"PA10": {"SIM_DET", "", "", "", "PA_EINT10"},
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"PA11": {"TWI0_SCK", "DI_TX", "", "", "PA_EINT11"},
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"PA12": {"TWI0_SDA", "DI_RX", "", "", "PA_EINT12"},
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"PA13": {"SPI1_CS", "UART3_TX", "", "", "PA_EINT13"},
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"PA14": {"SPI1_CLK", "UART3_RX", "", "", "PA_EINT14"},
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"PA15": {"SPI1_MOSI", "UART3_RTS", "", "", "PA_EINT15"},
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"PA16": {"SPI1_MOSI", "UART3_CTS", "", "", "PA_EINT16"},
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"PA17": {"OWA_OUT", "", "", "", "PA_EINT17"},
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"PA18": {"PCM0_SYNC", "TWI1_SCK", "", "", "PA_EINT18"},
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"PA19": {"PCM0_CLK", "TWI1_SDA", "", "", "PA_EINT19"},
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"PA20": {"PCM0_DOUT", "SIM_VPPEN", "", "", "PA_EINT20"},
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"PA21": {"PCM0_DIN", "SIM_VPPPP", "", "", "PA_EINT21"},
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"PC0": {"NAND_WE", "SPI0_MOSI"},
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"PC1": {"NAND_ALE", "SPI0_MISO"},
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"PC2": {"NAND_CLE", "SPI0_CLK"},
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"PC3": {"NAND_CE1", "SPI0_CS"},
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"PC4": {"NAND_CE0"},
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"PC5": {"NAND_RE", "SDC2_CLK"},
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"PC6": {"NAND_RB0", "SDC2_CMD"},
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"PC7": {"NAND_RB1"},
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"PC8": {"NAND_DQ0", "SDC2_D0"},
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"PC9": {"NAND_DQ1", "SDC2_D1"},
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"PC10": {"NAND_DQ2", "SDC2_D2"},
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"PC11": {"NAND_DQ3", "SDC2_D3"},
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"PC12": {"NAND_DQ4", "SDC2_D4"},
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"PC13": {"NAND_DQ5", "SDC2_D5"},
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"PC14": {"NAND_DQ6", "SDC2_D6"},
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"PC15": {"NAND_DQ7", "SDC2_D7"},
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"PC16": {"NAND_DQS", "SDC2_RST"},
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"PD0": {"RGMII_RXD3"},
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"PD1": {"RGMII_RXD2"},
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"PD2": {"RGMII_RXD1"},
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"PD3": {"RGMII_RXD0"},
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"PD4": {"RGMII_RXCK"},
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"PD5": {"RGMII_RXCTL"},
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"PD6": {"RGMII_NULL"},
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"PD7": {"RGMII_TXD3"},
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"PD8": {"RGMII_TXD2"},
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"PD9": {"RGMII_TXD1"},
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"PD10": {"RGMII_TXD0"},
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"PD11": {"RGMII_NULL"},
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"PD12": {"RGMII_TXCK"},
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"PD13": {"RGMII_TXCTL"},
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"PD14": {"RGMII_NULL"},
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"PD15": {"RGMII_CLKIN"},
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"PD16": {"MDC"},
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"PD17": {"MDIO"},
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"PE0": {"CSI_PCLK", "TS_CLK"},
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"PE1": {"CSI_MCLK", "TS_ERR"},
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"PE2": {"CSI_HSYNC", "TS_SYNC"},
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"PE3": {"CSI_VSYNC", "TS_DVLD"},
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"PE4": {"CSI_D0", "TS_D0"},
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"PE5": {"CSI_D1", "TS_D1"},
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"PE6": {"CSI_D2", "TS_D2"},
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"PE7": {"CSI_D3", "TS_D3"},
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"PE8": {"CSI_D4", "TS_D4"},
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"PE9": {"CSI_D5", "TS_D5"},
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"PE10": {"CSI_D6", "TS_D6"},
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"PE11": {"CSI_D7", "TS_D7"},
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"PE12": {"CSI_SCK", "TWI2_SCK"},
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"PE13": {"CSI_SDA", "TWI2_SDA"},
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"PE14": {""},
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"PE15": {""},
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"PF0": {"SDC0_D1", "JTAG_MS"},
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"PF1": {"SDC0_D0", "JTAG_DI"},
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"PF2": {"SDC0_CLK", "UART0_TX"},
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"PF3": {"SDC0_CMD", "JTAG_DO"},
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"PF4": {"SDC0_D3", "UART0_RX"},
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"PF5": {"SDC0_D2", "JTAG_CK"},
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"PF6": {"SDC0_DET"},
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"PG0": {"SDC1_CLK", "", "", "", "PG_EINT0"},
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"PG1": {"SDC1_CMD", "", "", "", "PG_EINT1"},
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"PG2": {"SDC1_D0", "", "", "", "PG_EINT2"},
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"PG3": {"SDC1_D1", "", "", "", "PG_EINT3"},
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"PG4": {"SDC1_D2", "", "", "", "PG_EINT4"},
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"PG5": {"SDC1_D3", "", "", "", "PG_EINT5"},
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"PG6": {"UART1_TX", "", "", "", "PG_EINT6"},
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"PG7": {"UART1_RX", "", "", "", "PG_EINT7"},
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"PG8": {"UART1_RTS", "", "", "", "PG_EINT8"},
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"PG9": {"UART1_CTS", "", "", "", "PG_EINT9"},
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"PG10": {"PCM1_SYNC", "", "", "", "PG_EINT10"},
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"PG11": {"PCM1_CLK", "", "", "", "PG_EINT11"},
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"PG12": {"PCM1_DOUT", "", "", "", "PG_EINT12"},
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"PG13": {"PCM1_DIN", "", "", "", "PG_EINT13"},
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"PL0": {"S_TWI_SCK", "", "", "", "S_PL_EINT0"},
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"PL1": {"S_TWI_SDA", "", "", "", "S_PL_EINT1"},
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"PL2": {"S_UART_TX", "", "", "", "S_PL_EINT2"},
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"PL3": {"S_UART_RX", "", "", "", "S_PL_EINT3"},
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"PL4": {"S_JTAG_MS", "", "", "", "S_PL_EINT4"},
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"PL5": {"S_JTAG_CK", "", "", "", "S_PL_EINT5"},
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"PL6": {"S_JTAG_DO", "", "", "", "S_PL_EINT6"},
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"PL7": {"S_JTAG_DI", "", "", "", "S_PL_EINT7"},
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"PL8": {"", "", "", "", "S_PL_EINT8"},
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"PL9": {"", "", "", "", "S_PL_EINT9"},
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"PL10": {"S_PWM", "", "", "", "S_PL_EINT10"},
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"PL11": {"S_CIR_RX", "", "", "", "S_PL_EINT12"},
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}
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// mapH3Pins uses mappingH3 to set the altFunc fields of all the GPIO pings and
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// mark them as available. This is called if the generic allwinner processor
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// code detects a H2+ or H3 processor.
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func mapH3Pins() error {
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for name, altFuncs := range mappingH3 {
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if strings.HasPrefix(name, "PL") {
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pinNumStr := name[2:]
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pinNum, err := strconv.Atoi(pinNumStr)
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if err != nil {
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return err
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}
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pin := &cpuPinsPL[pinNum]
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pin.available = true
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// Initializes the sysfs corresponding pin right away.
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pin.sysfsPin = sysfs.Pins[pin.Number()]
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} else {
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pin := cpupins[name]
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pin.altFunc = altFuncs
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pin.available = true
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if strings.Contains(string(altFuncs[4]), "_EINT") ||
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strings.Contains(string(altFuncs[3]), "_EINT") {
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pin.supportEdge = true
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}
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// Initializes the sysfs corresponding pin right away.
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pin.sysfsPin = sysfs.Pins[pin.Number()]
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}
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}
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return nil
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}
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