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// Copyright 2017 The Periph Authors. All rights reserved.
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// Use of this source code is governed under the Apache License, Version 2.0
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// that can be found in the LICENSE file.
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package bcm283x
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import (
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"errors"
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"fmt"
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"strings"
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"time"
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"periph.io/x/conn/v3/physic"
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)
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// errClockRegister is returned in a situation where the clock memory is not
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// working as expected. It is mocked in tests.
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var errClockRegister = errors.New("can't write to clock divisor CPU register")
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// Clock sources frequency in hertz.
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const (
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clk19dot2MHz = 19200 * physic.KiloHertz
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clk500MHz = 500 * physic.MegaHertz
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)
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const (
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// 31:24 password
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clockPasswdCtl clockCtl = 0x5A << 24 // PASSWD
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// 23:11 reserved
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clockMashMask clockCtl = 3 << 9 // MASH
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clockMash0 clockCtl = 0 << 9 // src_freq / divI (ignores divF)
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clockMash1 clockCtl = 1 << 9
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clockMash2 clockCtl = 2 << 9
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clockMash3 clockCtl = 3 << 9 // will cause higher spread
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clockFlip clockCtl = 1 << 8 // FLIP
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clockBusy clockCtl = 1 << 7 // BUSY
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// 6 reserved
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clockKill clockCtl = 1 << 5 // KILL
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clockEnable clockCtl = 1 << 4 // ENAB
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clockSrcMask clockCtl = 0xF << 0 // SRC
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clockSrcGND clockCtl = 0 // 0Hz
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clockSrc19dot2MHz clockCtl = 1 // 19.2MHz
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clockSrcTestDebug0 clockCtl = 2 // 0Hz
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clockSrcTestDebug1 clockCtl = 3 // 0Hz
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clockSrcPLLA clockCtl = 4 // 0Hz
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clockSrcPLLC clockCtl = 5 // 1000MHz (changes with overclock settings)
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clockSrcPLLD clockCtl = 6 // 500MHz
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clockSrcHDMI clockCtl = 7 // 216MHz; may be disabled
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// 8-15 == GND.
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)
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// clockCtl controls the clock properties.
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//
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// It must not be changed while busy is set or a glitch may occur.
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//
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// Page 107
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type clockCtl uint32
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func (c clockCtl) String() string {
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var out []string
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if c&0xFF000000 == clockPasswdCtl {
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c &^= 0xFF000000
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out = append(out, "PWD")
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}
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switch c & clockMashMask {
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case clockMash1:
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out = append(out, "Mash1")
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case clockMash2:
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out = append(out, "Mash2")
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case clockMash3:
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out = append(out, "Mash3")
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default:
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}
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c &^= clockMashMask
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if c&clockFlip != 0 {
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out = append(out, "Flip")
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c &^= clockFlip
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}
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if c&clockBusy != 0 {
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out = append(out, "Busy")
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c &^= clockBusy
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}
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if c&clockKill != 0 {
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out = append(out, "Kill")
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c &^= clockKill
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}
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if c&clockEnable != 0 {
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out = append(out, "Enable")
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c &^= clockEnable
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}
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switch x := c & clockSrcMask; x {
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case clockSrcGND:
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out = append(out, "GND(0Hz)")
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case clockSrc19dot2MHz:
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out = append(out, "19.2MHz")
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case clockSrcTestDebug0:
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out = append(out, "Debug0(0Hz)")
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case clockSrcTestDebug1:
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out = append(out, "Debug1(0Hz)")
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case clockSrcPLLA:
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out = append(out, "PLLA(0Hz)")
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case clockSrcPLLC:
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out = append(out, "PLLD(1000MHz)")
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case clockSrcPLLD:
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out = append(out, "PLLD(500MHz)")
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case clockSrcHDMI:
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out = append(out, "HDMI(216MHz)")
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default:
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out = append(out, fmt.Sprintf("GND(%d)", x))
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}
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c &^= clockSrcMask
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if c != 0 {
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out = append(out, fmt.Sprintf("clockCtl(0x%0x)", uint32(c)))
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}
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return strings.Join(out, "|")
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}
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const (
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// 31:24 password
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clockPasswdDiv clockDiv = 0x5A << 24 // PASSWD
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// Integer part of the divisor
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clockDiviShift = 12
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clockDiviMax = (1 << 12) - 1
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clockDiviMask clockDiv = clockDiviMax << clockDiviShift // DIVI
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// Fractional part of the divisor
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clockDivfMask clockDiv = (1 << 12) - 1 // DIVF
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)
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// clockDiv is a 12.12 fixed point value.
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//
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// The fractional part generates a significant amount of noise so it is
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// preferable to not use it.
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//
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// Page 108
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type clockDiv uint32
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func (c clockDiv) String() string {
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i := (c & clockDiviMask) >> clockDiviShift
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c &^= clockDiviMask
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if c == 0 {
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return fmt.Sprintf("%d.0", i)
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}
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return fmt.Sprintf("%d.(%d/%d)", i, c, clockDiviMax)
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}
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// clock is a pair of clockCtl / clockDiv.
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//
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// It can be set to one of the sources: clockSrc19dot2MHz(19.2MHz) and
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// clockSrcPLLD(500Mhz), then divided to a value to get the resulting clock.
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// Per spec the resulting frequency should be under 25Mhz.
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type clock struct {
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ctl clockCtl
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div clockDiv
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}
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// findDivisorExact finds the clock divisor and wait cycles to reduce src to
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// desired hz.
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//
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// The clock divisor is capped to clockDiviMax.
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//
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// Returns clock divisor, wait cycles. Returns 0, 0 if no exact match is found.
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// Favorizes high clock divisor value over high clock wait cycles. This means
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// that the function is slower than it could be, but results in more stable
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// clock.
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func findDivisorExact(src, desired physic.Frequency, maxWaitCycles uint32) (uint32, uint32) {
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if src < desired || src%desired != 0 || src/physic.Frequency(maxWaitCycles*clockDiviMax) > desired {
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// Can't attain without oversampling (too low) or desired frequency is
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// higher than the source (too high) or is not a multiple.
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return 0, 0
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}
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factor := uint32(src / desired)
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// TODO(maruel): Only iterate over valid divisors to save a bit more
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// calculations. Since it's is only doing 32 loops, this is not a big deal.
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for wait := uint32(1); wait <= maxWaitCycles; wait++ {
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if rest := factor % wait; rest != 0 {
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continue
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}
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clk := factor / wait
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if clk == 0 {
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break
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}
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if clk <= clockDiviMax {
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return clk, wait
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}
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}
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return 0, 0
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}
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// findDivisorOversampled tries to find the lowest allowed oversampling to make
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// desiredHz a multiple of srcHz.
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//
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// Allowed oversampling depends on the desiredHz. Cap oversampling because
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// oversampling at 10x in the 1Mhz range becomes unreasonable in term of
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// memory usage.
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func findDivisorOversampled(src, desired physic.Frequency, maxWaitCycles uint32) (uint32, uint32, physic.Frequency) {
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//log.Printf("findDivisorOversampled(%s, %s, %d)", src, desired, maxWaitCycles)
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// There are 2 reasons:
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// - desired is so low it is not possible to lower src to this frequency
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// - not a multiple, there's a need for a prime number
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// TODO(maruel): Rewrite without a loop, this is not needed. Leverage primes
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// to reduce the number of iterations.
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for multiple := physic.Frequency(2); ; multiple++ {
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n := multiple * desired
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if n > 100*physic.KiloHertz && multiple > 10 {
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break
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}
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if clk, wait := findDivisorExact(src, n, maxWaitCycles); clk != 0 {
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return clk, wait, n
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}
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}
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return 0, 0, 0
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}
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// calcSource choose the best source to get the exact desired clock.
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//
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// It calculates the clock source, the clock divisor and the wait cycles, if
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// applicable. Wait cycles is 'div minus 1'.
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func calcSource(f physic.Frequency, maxWaitCycles uint32) (clockCtl, uint32, uint32, physic.Frequency, error) {
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if f < physic.Hertz {
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return 0, 0, 0, 0, fmt.Errorf("bcm283x-clock: desired frequency %s must be >1hz", f)
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}
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if f > 125*physic.MegaHertz {
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return 0, 0, 0, 0, fmt.Errorf("bcm283x-clock: desired frequency %s is too high", f)
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}
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// http://elinux.org/BCM2835_datasheet_errata states that clockSrc19dot2MHz
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// is the cleanest clock source so try it first.
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div, wait := findDivisorExact(clk19dot2MHz, f, maxWaitCycles)
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if div != 0 {
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return clockSrc19dot2MHz, div, wait, f, nil
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}
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// Try 500Mhz.
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div, wait = findDivisorExact(clk500MHz, f, maxWaitCycles)
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if div != 0 {
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return clockSrcPLLD, div, wait, f, nil
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}
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// Try with up to 10x oversampling. This is generally useful for lower
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// frequencies, below 10kHz. Prefer the one with less oversampling. Only for
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// non-aliased matches.
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div19, wait19, f19 := findDivisorOversampled(clk19dot2MHz, f, maxWaitCycles)
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div500, wait500, f500 := findDivisorOversampled(clk500MHz, f, maxWaitCycles)
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if div19 != 0 && (div500 == 0 || f19 < f500) {
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return clockSrc19dot2MHz, div19, wait19, f19, nil
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}
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if div500 != 0 {
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return clockSrcPLLD, div500, wait500, f500, nil
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}
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return 0, 0, 0, 0, errors.New("failed to find a good clock")
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}
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// set changes the clock frequency to the desired value or the closest one
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// otherwise.
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//
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// f=0 means disabled.
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//
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// maxWaitCycles is the maximum oversampling via an additional wait cycles that
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// can further divide the clock. Use 1 if no additional wait cycle is
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// available. It is expected to be dmaWaitcyclesMax+1.
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//
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// Returns the actual clock used and divisor.
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func (c *clock) set(f physic.Frequency, maxWaitCycles uint32) (physic.Frequency, uint32, error) {
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if f == 0 {
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c.ctl = clockPasswdCtl | clockKill
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for c.ctl&clockBusy != 0 {
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}
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return 0, 0, nil
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}
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ctl, div, div2, actual, err := calcSource(f, maxWaitCycles)
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if err != nil {
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return 0, 0, err
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}
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return actual, div2, c.setRaw(ctl, div)
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}
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// setRaw sets the clock speed with the clock source and the divisor.
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func (c *clock) setRaw(ctl clockCtl, div uint32) error {
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if div < 1 || div > clockDiviMax {
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return errors.New("invalid clock divisor")
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}
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if ctl != clockSrc19dot2MHz && ctl != clockSrcPLLD {
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return errors.New("invalid clock control")
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}
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// Stop the clock.
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// TODO(maruel): Do not stop the clock if the current clock rate is the one
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// desired.
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for c.ctl&clockBusy != 0 {
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c.ctl = clockPasswdCtl | clockKill
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}
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d := clockDiv(div << clockDiviShift)
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c.div = clockPasswdDiv | d
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Nanospin(10 * time.Nanosecond)
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// Page 107
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c.ctl = clockPasswdCtl | ctl
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Nanospin(10 * time.Nanosecond)
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c.ctl = clockPasswdCtl | ctl | clockEnable
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if c.div != d {
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// This error is mocked out in tests, so the code path of set() callers can
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// follow on.
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return errClockRegister
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}
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return nil
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}
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func (c *clock) String() string {
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return fmt.Sprintf("%s / %s", c.ctl, c.div)
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}
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// clockMap is the memory mapped clock registers.
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//
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// The clock #1 must not be touched since it is being used by the ethernet
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// controller.
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//
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// Page 107 for gp0~gp2.
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// https://scribd.com/doc/127599939/BCM2835-Audio-clocks for PCM/PWM.
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type clockMap struct {
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reserved0 [0x70 / 4]uint32 //
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gp0 clock // CM_GP0CTL+CM_GP0DIV; 0x70-0x74 (125MHz max)
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gp1ctl uint32 // CM_GP1CTL+CM_GP1DIV; 0x78-0x7A must not use (used by ethernet)
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gp1div uint32 // CM_GP1CTL+CM_GP1DIV; 0x78-0x7A must not use (used by ethernet)
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gp2 clock // CM_GP2CTL+CM_GP2DIV; 0x80-0x84 (125MHz max)
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reserved1 [(0x98 - 0x88) / 4]uint32 // 0x88-0x94
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pcm clock // CM_PCMCTL+CM_PCMDIV 0x98-0x9C
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pwm clock // CM_PWMCTL+CM_PWMDIV 0xA0-0xA4
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}
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func (c *clockMap) GoString() string {
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return fmt.Sprintf(
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"{\n gp0: %s,\n gp1: %s,\n gp2: %s,\n pcm: %sw,\n pwm: %s,\n}",
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&c.gp0, &clock{clockCtl(c.gp1ctl), clockDiv(c.gp1div)}, &c.gp2, &c.pcm, &c.pwm)
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}
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